1. Field of Invention
The present invention relates to a semiconductor device, especially to a resistance element.
2. Description of the Related Art
FIGS. 1 and 2 show a resistance element of prior art with FIG. 1 being its cross sectional view and FIG. 2 being its view from a slanting angle. A resistance element 27 is formed by patterning a polycrystalline silicon film 2 on a single crystal silicon substrate. The resistance element 27 comprises a resistor 20, whose resistance value is determined by its length L, width W and height (or thickness) T and the concentration of impurities, and contact regions 21 on both sides of the resistor.
FIGS. 3 and 4 show a resistance element of prior art with FIG. 3 being its cross sectional view and FIG. 4 being its top view. In a single crystal silicon substrate of first conduction type, a resistance element 37 of second conduction type is formed by diffusing impurities of second conduction type. The resistance element 37 comprises a resistor 30, whose resistance value is determined by its length L, width W and the concentration of impurities, and contact regions 31 on both side of the resistor.
Another resistance element of prior art as shown in FIG. 5 is disclosed in Japanese Unexamined Publication TOKKAI SHO 2-283058. In FIG. 5, a resistance element 47 is formed by patterning a non-doping polycrystalline silicon film grown by CVD method and introducing impurities into the area on an insulation film 2. The resistance element 47 comprises a resistor 40 and contact regions 41 on both side of the resistor. The contact region 41 and a non-doping region of the single crystal silicon film 42, which is formed gradually, are connected to the single crystal silicon substrate 1 in an opening 43 which is formed on the insulation film, so that the radiation can be improved by radiating to the single crystal silicon substrate through the non-doping region 42.
The resistance elements of the above mentioned FIGS. 1-5 have the following unsolved problems;
First, a resistance element shown in FIGS. 1 and 2 is formed on an insulation film, therefore, the degree of integration on the silicon substrate, where other elements are formed, can be improved. However, because the configuration of the resistance element 27 is formed by patterning the polycrystalline silicon film by etching, the resistance value is apt to largely vary depending on variance of the measurement due to etching. For example, when T is 200 .mu.m and the width of the mask is 0.6 .mu.m, W becomes 0.4 to 0.6 .mu.m, making the resistance value vary .+-.20%. Furthermore, because the radiation routes of the heat generated at the resistor 20 in the resistance element 27 are the one to the wiring connected through the contact region 21 and the other through the insulation film 2 at the bottom side, the radiation is of problem.
In case of the resistance element shown in FIGS. 3 and 4, because the configuration of the resistance element can be formed by introducing impurities by using photoresist as a mask, the variance of the configuration is minimized and the same of the resistance value is also minimized. The radiation is also good in this structure. However, because it is formed in the silicon substrate where other elements are also formed, the improvement of the degree of integration of the silicon substrate is limited. Also, because the parasitic capacity due to a PN junction formed with the silicon substrate is large, hindrance for high speed operation is apt to occur. The insulation also become of problem.
In case of the resistance element shown in FIG. 5, although radiation can be improved, as the configuration of the resistance element, i.e. the configuration of the width direction is formed by selective etching, the variance of the resistance value is apt to become large as in the case of FIGS. 1 and 2. Also, improvement of the degree of integration of the silicon substrate is limited because it requires an opening 43 to have the substrate exposed. Furthermore, the polycrystalline silicon film is deposited by CVD method. Because the particle size of polycrystalline silicon by CVD method is so large as 0.01 to 0.05 .mu.m that the resistance value varies greatly between before and after the activation heat treatment which takes place after the ion implantation of impurities. For example, the resistance value before and after the activation heat treatment varies by 50%, and the variance of the varied values is as large as 30%. Therefore, there is a defect that the final resistance value is difficult to pre-determine.
Another example of variation of the conventional manufacturing method of a semiconductor device shown in FIG. 5 is to form a resistance element by heat treatment of amorphous silicon formed by using the surface portion of the single crystal silicon exposed in the opening 43 as a seed. In the case of this method, because single crystal silicon develops in the opening 43, the amorphous silicon closer to the opening on the insulation film 2 is converted to single crystal silicon resulting in a state that the more polycrystalline silicon exists at the farther site from the opening. Therefore, because the particle size as a whole becomes larger, the problem of the variance of the values between before and after the heat treatment does not occur. However, the state of the crystallization varies depending on the distance from the opening 43. Because the resistance characteristic differs between the resistance element formed on single crystal silicon and the one formed on polycrystalline silicon, the factor of distance of the resistance element has to be taken into consideration when designing the arrangement, making the design very complex. Also, even if the method is modified as described above, the variation of the resistance value due to varied configuration in the width direction and the limitation on the degree of integration on the single crystal silicon substrate due to requirement for an opening remain as problems just as in FIG. 5.